The present invention relates generally to electronic components such as multilayer glass ceramic chip modules and more particularly, to differential wiring patterns in the multilayer glass ceramic chip modules.
As integrated circuit (IC) technology advances towards large-scale integration and high performance multilayer multi-chip modules (MCMs), it is necessary to provide MCM interconnect packaging that is compatible with the demands of the associated circuitry. In other words, the reduction of signal delay, package impedance, and cross-talk in the wiring of MCM packaging has become extremely important. Present day packaging used in MCMs is typically made of multiple layers of glass-ceramics (hereinafter “ceramics”), commonly referred to as multilayer ceramic (MLC) modules. MLC modules are typically composed of multiple layers of ceramics, or other insulating material of relatively high thermal conductivity with conductors formed on the respective surfaces and through-holes (via) formed through the layers.
In general, a MLC module is formed by stacking and bonding together flexible sheets of ceramic material, commonly referred to as ceramic greensheets. Greensheet segments of a desired size and configuration may be pre-punched to provide via holes and, may be patterned, typically by a screen printing technique, with a conductive paste that creates a conductive circuit pattern on the surface of the greensheet as well as fills the via holes to form interlayer contact lines. Patterned greensheets are assembled in a stack, pressed, and subsequently sintered in an oven at a relatively high temperature. Upon sintering, organics, such as binders, dispersants, plasticizers, thixotropes, solvents, etc., are burned off providing a rigid unitary ceramic body having interior interconnected conductive patterns.
Typically, the wiring in a MLC module is laid out in a meshed plane (i.e., repeating pairs of horizontal lines connected to repeating pairs of vertical interlayer lines that form a structure resembling repeating cubes). This mesh pattern may result in significant vertical coupling between signal lines. A common solution to this problem is to include a blank layer between each layer of horizontal lines to provide additional insulation. However, as the need for higher bandwidth at low cost has increased, the reduction of the overall number of layers in carriers has become a priority. Unfortunately, eliminating the blank layer to minimize vertical density results in poor signal to crosstalk ratio at high frequencies and limits the viability of this packaging technology for high baud rates.